1. Field of the Invention
The present invention relates to a signal transmission system and a receiver circuit for use in the signal transmission system, and more particularly, to a signal transmission system for transmitting signals between LSI chips and a receiver circuit for use in the same.
2. Description of the Related Art
Recently, DRAM (Dynamic Random Access Memory) and processor performances have improved dramatically, and more specifically, processor performance has improved rapidly in terms of speed, while the improvement of DRAM performance has been dramatic primarily in terms of storage capacity. However, the improvement in operating speed of DRAM has not been so dramatic as the increase in storage capacity, as a result of which the speed gap between DRAM and processor has widened and this speed gap has become a bottleneck in boosting computer performance in recent years.
Among the signal transmission systems for signal transmission between processors and DRAMs (DRAM modules) known in the prior art and expected to find widespread use in the next few years are the SSTL (Series-Stub Terminated Logic) and other low-amplitude signaling standards. In the SSTL (or in a similar low-amplitude signaling system), a signal transmission line (hereinafter the transmission line) is terminated in a resistance close to the characteristic impedance of the transmission line, thereby suppressing reflections at its terminating ends and achieving high signal transmission speeds. Furthermore, by using low-amplitude signaling, the power required to charge and discharge the transmission line is reduced, making low-power transmission possible in high-speed operation.
In a bus system (signal transmission system) employing the SSTL, high-speed signal transmission is made possible because of matched termination (terminal resistance) and stub resistance, and power consumption also is reduced compared to traditional systems because of the use of low-amplitude signaling. However, in order to maintain the overall power consumption of the apparatus at the current level, or reduce it below the current level, while increasing the signal transmission bandwidth between DRAM and processor, a signal transmission system with lower power consumption is demanded.
Further, for example, in a Rambus channel, a DRAM controller and a plurality of DRAM chips are interconnected by a common signal transmission line (bus). For transmission and reception of high-speed signals, precise timing must be established between the signal sender and receiver. In the Rambus channel, correct timing can be established for both reception and transmission, provided that a clock line and a signal transmission line are identical both in routing and in electrical characteristics. That is, the Rambus channel requires that the clock line and the signal transmission line be formed along the same route and have the same electrical characteristics between them.
However, the characteristic of the load is inevitably different between the clock line and the signal transmission line. This is because, while the signal transmission line permits the use of a latch circuit operating in synchronism with receive timing to achieve high-sensitivity reception, the clock line requires the use of a differential amplifier, etc. since a latch cannot be used. Since the nature of the load is different between a latch circuit and a differential amplifier and the like, line electrical characteristics (for example, delay per unit distance), etc. are bound to become different between the clock line and the signal transmission line.
The prior and related arts, and their associated problems will be described in detailed later with reference to the accompanying drawings
It is an object of the present invention to provide a signal transmission system wherein the response time of a signal transmission line is set approximately equal to or longer than the length of a transmitted symbol. It is another object of the present invention to provide a signal transmission system that can generate timing signals without demanding symmetry between the clock line and the signal transmission line (bus), and that can minimize the gap when switching is made from one transmitting device to another.
According to the present invention, there is provided a signal transmission system wherein the response time of a signal transmission line is set approximately equal to or longer than the length of a transmitted symbol.
A terminal resistance provided at one or both ends of the signal transmission line may be set larger than a characteristic impedance of the signal transmission line. At least one resistor may be provided in series with the signal transmission line or the signal transmission line may be constructed to contain resistance in itself.
Signals may be transmitted between a plurality of circuit blocks. At least one of the plurality of circuit blocks may have a receiver circuit for receiving a signal transmitted out on the signal transmission line, and the receiver circuit may comprise a partial-response detection unit for detecting a partial response that the signal shows, and a signal logic decision unit for making a logic decision on the signal. The partial-response detection unit may comprise an intersymbol interference estimation unit for estimating intersymbol interference based on a previously received signal and a subtracting unit for subtracting the estimated intersymbol interference from a signal in effect currently received.
The intersymbol interference estimation unit may be constructed to obtain a sum of linear weights of previous decision values. The intersymbol interference estimation unit may comprise a shift register for holding previous bit information and a weighting unit for weighting data held in the shift register. The weighting unit may be constructed from a plurality of resistors. The weighting unit may be constructed from a plurality of capacitors and switches.
The intersymbol interference estimation unit may ba constructed to obtain nonlinear weights of previous decision values. The intersymbol interference estimation unit may comprise a shift register for holding previous bit information and a memory unit for storing estimates corresponding to data held in the shift register.
The intersymbol interference estimation unit may comprise an accumulating unit for accumulating an analog value of the previously received signal and an intersymbol interference generating unit for generating intersymbol interference from the analog value. The intersymbol interference estimation unit may be constructed to take a linear weighted sum of an analog value of a signal received one clock back and a fixed reference analog value. The intersymbol interference estimation unit may be provided with a plurality of switch units and capacitor units.
The plurality of circuit blocks may be semiconductor integrated circuit chips, and the signal transmission system may be configured as a bus system interconnecting the plurality of semiconductor integrated circuit chips. The signal transmission line may be configured as a bidirectional data bus or data signal line. The signal transmission line may be configured as a unidirectional address bus or address signal line. The plurality of semiconductor integrated circuit chips may be constructed with a processor or controller and a plurality of memory modules.
Further, according to the present invention, there is provided a signal transmission system for transmitting a signal between a plurality of circuit blocks via a signal transmission line, comprising a clock distribution unit for distributing a clock to each of the circuit blocks via a clock line; a common timing signal generating unit for providing common timing based on the clock to each of the circuit blocks with an accuracy of; time shorter than the time required for the signal to travel through wiring between the circuit blocks; and a unit for transmitting and receiving the signal in synchronism with the common timing.
Each of the circuit blocks may be an integrated circuit module, an integrated circuit chip, or a constituent circuit within a single chip. The maximum length of the signal transmission line may be not greater than the distance that the signal travels along the signal transmission line in one bit time. The maximum length of the signal transmission line may be not greater than half the distance that the signal travels along the signal transmission line in one bit time.
There may be inserted in the signal transmission line a buffer for giving the signal a delay equal to an integral multiple of one bit time of the signal and for retransmitting the delayed signal, the buffer thus enabling the signal to be transmitted over a distance exceeding the maximum length of the signal transmission line. The buffer may output to other circuit blocks connected via the buffer a clock necessary for the other circuit blocks to generate common timing.
The signal transmission line may be a bus of a common signal line type, and may be provided at one end or both ends of the bus with a terminal resistor having resistance approximately equal to or greater than the characteristic impedance of the bus. A driver circuit for driving the signal transmission line may have an output impedance greater than the characteristic impedance of the signal transmission line. The driver circuit may produce a constant-current driving output.
The common timing signal generating unit may capture clocks travelling along a clock line folded between a forward section and a backward section, and may generate the common timing by taking a timing intermediate between the rising timings of the forward and backward travelling clocks captured by each circuit block. The common timing signal generating unit may comprise a linear sum generating unit for generating a linear sum of sinusoidal clocks on the forward and backward sections of the folded clock line, and a waveform shaping unit for waveform-shaping the sine waves obtained by the linear sum generating unit. The common timing signal generating unit may comprise a phase interpolator for capturing the forward and backward travelling clocks on the folded clock line, and for generating a clock having a phase intermediate between the forward and backward travelling clocks.
The common timing signal generating unit may produce a standing wave along the clock line, and each of the circuit blocks may capture the clock from the standing wave produced along the clock line. A producing unit for producing the standing wave along the clock line may include a creating unit for actively creating a reflected signal of the clock in either a clock driving circuit or a clock terminating circuit or both, thereby adjusting an electrical length of the clock line.
The cycle of the clock used to generate the common timing may be longer than two times the length of one bit time of the signal transmitted along the signal transmission line. The clock line may have a transmission characteristic substantially different from the signal transmission line, and may be provided with increased electrical shielding against an external environment compared to the signal transmission line.
At least one of the circuit blocks may be provided at a receiving side thereof with a receiver- circuit for eliminating intersymbol interference from the signal, and may receive the signal transmitted via the signal transmission line.
In addition, according to the present invention, there is also provided a receiver circuit, for use in a signal transmission system, for receiving a signal transmitted on a signal transmission line, the receiver, circuit comprising a partial-response detection unit for detecting a partial response that the signal shows, and a signal logic decision unit for making a logic decision on the signal
The partial-response detection unit may comprise an intersymbol interference estimation unit for estimating intersymbol interference based on a previously received signal and a subtracting unit for subtracting the estimated intersymbol interference from a signal in effect currently received. The intersymbol interference estimation unit may be constructed to obtain a sum of linear weights of previous decision values. The intersymbol interference estimation unit may comprise a shift register for holding previous bit information and a weighting unit for weighting data held in the shift register. The weighting unit may be constructed from a plurality of resistors. The weighting unit may be constructed from a plurality of capacitors and switches.
The intersymbol interference estimation unit may be constructed to obtain nonlinear weights of previous decision values. The intersymbol interference estimation unit may comprise a shift register for holding previous bit information and a memory unit for storing estimates corresponding to data held in the shift register.
The intersymbol interference estimation unit may comprise an accumulating unit for accumulating an analog value of the previously received signal and an intersymbol interference generating unit for generating intersymbol interference from the analog value. The intersymbol interference estimation unit may be constructed to take a linear weighted sum of an analog value of a signal received one clock back and a fixed reference analog value. The intersymbol interference estimation unit may be provided with a plurality of switch units and capacitor units.
The common timing signal generating unit may capture a forward clock and a backward clock travelling along a forward clock line and a backward clock line, and may; generate the common timing by taking a timing intermediate between the rise or fall timings of the forward and backward travelling clocks captured by each circuit block. At least one pair of clock generating circuits including a forward clock generating circuit and a backward clock generating circuit may be provided for each clock line pair including the forward clock line and the backward clock line, and the forward clock and backward clock generating circuits may adjust the phases of the rising or falling edges of the forward and backward clocks to set the phases at prescribed values. The forward clock generating circuit may comprise a unit for synchronizing the timing of an intermediate-phase signal, obtained by extracting an intermediate point between the rise or fall timings of the forward and backward clocks, to the rise or fall timing of a reference clock, a unit for detecting a phase difference between the intermediate-phase signal and the common timing signal, and a unit for adjusting the phase of the forward clock so that the detected phase difference becomes zero.
A plurality of clock generating circuits may be provided for the each forward/backward clock line pair, and wherein the clock generating circuit located at each end of the forward/backward clock line pair may comprise only a forward clock generating circuit or a backward clock generating circuit, and each of the clock generating circuits located at intermediate positions along the forward/backward may comprise a backward clock generating circuit, which generates a common timing signal and a backward clock on the basis of the forward clock received from the clock generating circuit at the preceding stage, and a forward clock generating circuit, which generates a new forward clock for the clock generating circuit at the next stage. Each of the clock generating circuits may further include a buffer for driving a signal supplied via a signal line. The signal line connecting between the circuit blocks may be connected point-to-point, and the clock generating circuits may be provided one for every one or multiples of the circuit blocks.
The backward clock generating circuit may be constructed from a feedback loop which performs a phase adjustment to maintain a constant phase difference between the received forward clock and the backward clock. The backward clock generating circuit may be constructed with a variable delay unit, a feedback loop for synchronizing a delay amount in the variable delay unit to a clock cycle, and a unit for giving the forward clock a delay amount proportional to the clock cycle by a delay stage controlled subordinately to the feedback loop. The variable delay unit may comprise a plurality of variable delay circuits in cascade, the feedback loop may control the delay amount in each of the variable delay circuits at the same value, and the backward clock may be taken from a designated node along the plurality of variable delay circuits.
The phase of the backward clock may be controlled so that the phase difference between the forward clock and an inverted version of the backward clock falls within xc2x1180 or xc2x190 degrees at any of the circuit blocks receiving the forward and backward clocks.
The backward clock may be an inverted version of the forward clock. The forward and backward clocks each may have a waveform whose rise and fall times constitute a significant proportion of a clock cycle. The forward and backward clocks each may have a sinusoidal, triangular, or trapezoidal waveform. The common timing signal generating circuit may be a differential comparator to which the forward and backward clocks are applied as differential inputs.
Terminating ends of the forward and backward clock lines may be each terminated with an impedance greater than the characteristic impedance of the forward and L backward clock lines. At least either one of the forward and backward clocks may be transmitted using a differential signal transmission method. The forward clock may be transmitted as complementary signals, and the backward clock may be generated from a signal created by differentially amplifying the complementary forward clocks.
The forward and backward clocks may be generated by introducing a delay amount given by a feedback-controlled variable delay circuit into a reference clock in a free-running state. When capturing the forward and backward clocks, a signal once output outside a chip may be latched again into the chip as the forward clock, based on which the common timing signal is generated.
According to the present invention, there is provided a signal transmission system comprising a signal transmission line configured to transmit data without requiring precharging for every bit, by eliminating an intersymbol interference component introduced by preceding data; and a unit for eliminating an intersymbol interference component of a signal transmitted via the signal transmission line.
The signal transmission line may be constructed in a single-ended configuration. The signal transmission line may be configured as complementary buses, and the signal transmission system may include a complementary-type bus driver and a complementary-type bus amplifier.
The signal transmission system may further comprise a precharge circuit which does not precharge the signal transmission line for every bit during a data transmission period, and which precharges the signal transmission line to a prescribed potential level except during the data transmission period. The precharge circuit may precharge the signal transmission line only during a prescribed period before and after the data transmission period. The precharge circuit may precharge the signal transmission line during all periods other than the data transmission period. The precharge circuit may precharge the signal transmission line arbitrarily from outside.
The complementary-type bus amplifier may comprise an amplifier with an intersymbol interference elimination function for a single-ended line corresponding to each of the complementary buses, and a complementary-type differential amplifier provided on the downstream side of the amplifier with the intersymbol interference elimination. The complementary-type differential amplifier may be configured as a latch-type differential amplifier. The latch-type differential amplifier may be configured as a gate-receiving differential amplifier. The complementary-type differential amplifier may be configured as a current-mirror type differential amplifier.
The complementary-type bus amplifier may comprise a differential amplifier having first and second gate-receiving complementary inputs; an amplifier precharging circuit, provided at each of the first and second inputs of the differential amplifier, for precharging in a manner that enhances the sensitivity of the differential amplifier; and two sets of first and second capacitors provided at the first and second inputs of the differential amplifier, wherein the first and second inputs of the differential amplifier may be coupled to the complementary buses via the first and second capacitors, and in each set of capacitors the first capacitor may be coupled at all times to one of the complementary buses, whereas the second capacitor may be selectively coupled by switch means to one or the other of the complementary buses.
In each set of capacitors, the second capacitor may be coupled, during an intersymbol interference estimation operation, to the bus opposite to the bus coupled to the first capacitor connected to the same differential input, and may be coupled, during a data decision operation, to the same bus that is coupled to the first capacitor connected to the same differential input, thereby achieving elimination of complementary intersymbol interference components. The complementary-type bus amplifier may comprise first and second amplifier blocks each having an intersymbol interference elimination function, and may be configured so that the second amplifier block performs a data decision operation while the first amplifier block is performing an intersymbol estimation operation, and at the next timing, performs an intersymbol interference estimation operation while the first amplifier block is performing a data decision operation, and wherein the first and second amplifier blocks may each comprise a differential amplifier having first and second gate-receiving complementary inputs; an amplifier precharging circuit, provided at each of the first and second inputs of the differential amplifier, for precharging in a manner that enhances the sensitivity of the differential amplifier; and two sets of first and second capacitors provided at the first and second inputs of the differential amplifier, wherein the first and second inputs of the differential amplifier may be coupled to the complementary buses via the first and second capacitors, and in each set of capacitors the first capacitor may be coupled at all times to one of the complementary buses, whereas the second capacitor may be selectively coupled by a switch unit to one or the other of the complementary buses.
The complementary-type bus amplifier may comprise a differential amplifier having first and second gate-receiving complementary inputs; an amplifier precharging circuit, provided at the first input of the differential amplifier, for precharging in a manner that enhances the sensitivity of the differential amplifier; an auto-zero circuit for controlling electrical conduction between the second input of the differential amplifier and an output of the differential amplifier; and two sets of first and second capacitors provided at the first and second inputs of the differential amplifier, wherein the first and second inputs of the differential amplifier may be coupled to the complementary buses via the first and second capacitors, and in each set of capacitors the first capacitor may be coupled at all times to one of the complementary buses, whereas the second capacitor may be selectively coupled by switch means to one or the other of the complementary buses. In each set of capacitors, the second capacitor may be coupled, during an intersymbol interference estimation operation, to the bus opposite to the bus coupled to the first capacitor connected to the same differential input, and may be coupled, during a data decision operation, to the same bus that is coupled to the first capacitor connected to the same differential input, thereby achieving elimination of complementary intersymbol interference components.
The complementary-type bus amplifier may comprise first and second amplifier blocks each having an intersymbol interference elimination function, and may be configured so that the second amplifier block performs a data decision operation while the first amplifier block is performing an intersymbol estimation operation, and at the next timing, performs an intersymbol interference estimation operation while the first amplifier block is performing a data decision operation, and wherein the first and second amplifier blocks each may comprise a differential amplifier having first and second gate-receiving complementary inputs; an amplifier precharging circuit, provided at the first input of the differential amplifier, for precharging in a manner that enhances the sensitivity of the differential amplifier; an auto-zero circuit for controlling electrical conduction between the second input of the differential amplifier and an output of the differential amplifier; and two sets of first and second capacitors provided at the first and second inputs of the differential amplifier, wherein the first and second inputs of the differential amplifier may be coupled to the complementary buses via the first and second capacitors, and in each set of capacitors the first capacitor may be coupled at all times to one of the complementary buses, whereas the second capacitor may be selectively coupled by switch means to one or the other of the complementary buses.
In each set of capacitors, the second capacitor may be coupled, during the intersymbol interference estimation operation, to the bus opposite to the bus coupled to the first capacitor connected to the same differential input, and may be coupled, during the data decision operation, to the same bus that is coupled to the first capacitor connected to the same differential input, thereby achieving elimination of complementary intersymbol interference components. When the value of the first capacitor is denoted by C10, and the value of the second capacitor by C20, the values of the first and second capacitors may be chosen to substantially satisfy the equation C10/(C10+C20)=(1+exp(xe2x88x92T/xcfx84))/2, where xcfx84 is the time constant of the bus, and T is the cycle of one bit or the time one-bit data appears on the bus.
The differential amplifier may be configured as a latch-type differential amplifier. Except during a data read period, the differential amplifier may set an output node thereof at a high level when a data receiving transistor is an N-channel type, or at a low level when the data receiving transistor is a P-channel type, thereby increasing the operating speed. During a differential amplifier input node precharge operation and an intersymbol interference component estimation operation within a data read period, and except during a data transfer period, the differential amplifier may set an output node thereof at a high level when a data receiving transistor is an N-channel type, or at a low level when the data receiving transistor is a P-channels type, thereby increasing operating speed. The differential amplifier may be configured as a current-mirror type differential amplifier. The differential amplifier may be configured so as not to operate except during a data transfer period.
The complementary-type bus amplifier may be a data bus amplifier, the complementary-type bus driver may be a sense amplifier, and the complementary buses may be data buses, respectively, wherein the data bus amplifier may remove an intersymbol interference component contained in data transmitted from the sense amplifier via the data buses and thereby may perform uninterrupted data read without precharging the data buses during data transmission.
The semiconductor memory device may be a dynamic random-access memory. The data buses may be organized in a hierarchical structure. The data buses may comprise a local data bus for transmitting data output from the sense amplifier via a selected column transfer gate, and a global data bus for transmitting data transferred from the local data bus via a selected local data bus switch.
The data bus amplifier may read out data by operating two amplifier blocks, provided in parallel and equipped with an intersymbol interference elimination function, in interleaving fashion in synchronism with the rise and fall timings of a clock or the rise timings of complementary clocks. The semiconductor memory device may further comprise a first column-selection signal generating unit, having a column decoder and a column-selection signal generating circuit, for generating a column-selection signal from the rise timing of the clock; and a second column-selection signal generating unit, having a column decoder and a column-selection signal generating circuit, for generating a column-selection signal from the fall timing of the clock or the rise timing of an inverted clock, and wherein the first: and the second column-selection signal generating units may be operated in interleaving fashion to perform switching between the column-selection signals at high speed. The first and the second column-selection signal generating units may generate the column-selection signals in overlapping fashion.
The data bus amplifier may read out data by using a single amplifier block equipped with an intersymbol interference elimination function. The amplifier block equipped with the intersymbol interference elimination function may perform an intersymbol interference component estimation operation in synchronism with the rise or fall timing of a clock, and a data decision operation in synchronism with the fall or rise timing of the clock.
The semiconductor device may include a load provided for the data buses. In cases where the data buses tend to shift gradually toward a low level side in the absence of the load, the load may be constructed with a P-channel MOS transistor of a size just sufficient to suppress the shift of the data buses, and the complementary buses may be respectively pulled to a high level through the P-channel MOS transistor, and wherein except during data transmission, the P-channel MOS transistor may be turned off to stop the action of the load. In cases where the data buses tend to shift gradually toward a low level side in the absence of the load, the load may be constructed with an N-channel MOS transistor of a size just sufficient to suppress the shift of the data buses, and the complementary buses may be respectively pulled to a high level through the N-channel MOS transistor, and wherein except during data transmission, the N-channel MOS transistor may be turned off to stop the action of the load.
In cases where the data buses tend to shift gradually toward a low level side in the absence of the load, the load may be constructed with a resistor, and the resistor may be connected to a high level via a transistor, and wherein except during data transmission, the transistor may be turned off to stop the action of the load. In cases where the data buses tend to shift gradually toward a low level side in the absence of the load, the load may be constructed with cross-coupled P-channel MOS transistors, and the cross-coupled P-channel MOS transistors may be connected to a high level via a control transistor so that one bus transmitting high-level data may be pulled to a higher level than the other bus transmitting low-level data, and wherein except during data transmission, the control transistor may be turned off to stop the action of the load. In cases where the data buses tend to shift gradually toward a high level side in the absence of the load, the load may be constructed with an N-channel MOS transistor of a size just sufficient to suppress the shift of the data buses, and the complementary buses may be respectively pulled to a low level through the N-channel MOS transistor, and wherein except during data transmission, the N-channel MOS transistor may be turned off to stop the action of the load.
In cases where the data buses tend to shift gradually toward a high level side in the absence of the load, the load may be constructed with a P-channel MOS transistor of a size just sufficient to suppress the shift of the data buses, and the complementary buses may be respectively pulled to a low level through the P-channel MOS transistor, and wherein except during data transmission, the P-channel MOS transistor may be turned off to stop the action of the load. In cases where the data buses tend to shift gradually toward a high level side in the absence of the load, the load may be constructed with a resistor, and the resistor may be connected to a low level via a transistor, and wherein except during data transmission, the transistor may be turned off to stop the action of the load. In cases where the data buses tend to shift gradually toward a high level side in the absence of the load, the load may be constructed with cross-coupled N-channel MOS transistors, and the cross-coupled N-channel MOS transistors may be connected to a low level via a control transistor so that one bus transmitting low-level data may be pulled to a lower level than the other bus transmitting high-level data, and wherein except during data transmission, the control transistor may be turned off to stop the action of the load.
The load may be provided only at one place on the global data bus. Multiples of the load may be provided spaced apart from one another at a plurality of places along the global data bus. The load may be provided only on the local data bus. Multiples of the load may be provided spaced apart from one another at a plurality of places along the global data bus and the local data bus. The sense amplifier may be configured as a CMOS transistor cross-coupled pair. The sense amplifier may receive a differential potential on a bit line by a gate, and may transfer data onto the data buses before the bit line is fully opened, thereby preventing the data in the sense amplifier from being inverted by the differential potential of the data buses.
The sense amplifier may be configured as a P-channel or N-channel MOS transistor gate-receiving amplifier. The sense amplifier may be configured as a CMOS transistor gate-receiving amplifier. The semiconductor memory device may compensate a skew, which is determined from a time of generating a column-selection signal for selecting a sense amplifier to a time of arriving data output from the selected sense amplifier at the bus amplifier, due to a position of the selected sense amplifier, and may determine control signals used in the data bus amplifier at an appropriate timing where the arrived data are effective, the skew being caused by a difference between a first length from a column-selection signal generating circuit to the selected sense amplifier and a second length from the selected sense amplifier to the data bus amplifier via the data bus.
The semiconductor memory device may generate the column-selection signal at later timing for sense amplifiers located nearer to the column-selection signal generating circuit and the data bus amplifier and at earlier timing for sense amplifiers located farther from the column-selection signal generating circuit and the data bus amplifier, thereby keeping the timing where data arrive at the bus amplifier substantially constant irrespective of the location of each of the sense amplifiers. The semiconductor memory device may be divided into a plurality of memory blocks crossing to a longitudinal direction of the data bus directly connected to the data bus amplifier, a block-selection address for selecting the memory block may be input to the column-selection signal generating circuit, a delay amount in the column-selection signal generating circuit may be controlled by the block-selection address, and thereby the timing where data arrive at the bus amplifier may be substantially constant irrespective of the location of each of the sense amplifiers.
The semiconductor memory device may supply a row block-selection address to a column-selection signal generating circuit, and a delay amount in the column-selection signal generating circuit may be controlled by the block-selection address in such a manner that the generating timing for the column-selection signal is advanced for blocks located farther from the bus amplifier and is delayed for blocks located nearer to the bus amplifier. The delay amount in the column-selection signal generating circuit may be formed by a transfer gate and added capacitance, the value of the added capacitance being made greater for blocks located nearer to the bus amplifier. The delay amount in the column-selection signal generating circuit may be formed by a delay line consisting of a plurality of cascaded delay stages, the delay line providing a larger number of delay stages to be passed through for block nearer to the bus amplifier. Each of the delay stages may comprise first and second NAND gates and an inverter.
The semiconductor memory device may generate control signals used in the data bus amplifier at earlier timing for sense amplifiers located nearer to the column-selection signal generating circuit and the data bus amplifier and at later timing for sense amplifiers located farther from the column-selection signal generating circuit and the data bus amplifier, and may determine the control signals used in the data bus amplifier at an appropriate timing where the arrived data are effective.
Further, according to the present invention, there is provided a receiver circuit for use in a signal transmission system that transmits data via complementary buses, and that detects the data by eliminating an intersymbol interference component introduced by preceding data, comprising a differential amplifier having first and second gate-receiving complementary inputs; an amplifier precharging circuit, provided at each of the first and second inputs of the differential amplifier, for precharging in a manner that enhances the sensitivity of the differential amplifier; and two sets of first and second capacitors provided at the first and second inputs of the differential amplifier, wherein the first and second inputs of the differential amplifier are coupled to the complementary buses via the first and second capacitors, and in each set of capacitors the first capacitor is coupled at all times to one of the complementary buses, whereas the second capacitor is selectively coupled by a switch unit to one or the other of the complementary buses.